The present invention relates to a method for producing a trench transistor and to a trench transistor.
Although applicable in principle to arbitrary integrated circuits, the present invention and also the problems on which it is based will be explained with regard to integrated memory circuits in silicon technology.
Published U.S. application for patent No. 2005/0042833 A1 discloses a method for fabricating an integrated circuit device comprising a trench transistor. The conventional method has the following steps of: defining an active region by forming a trench device isolation region on an integrated circuit substrate; forming a mask pattern on the integrated circuit substrate that uncovers a channel sub-region of the active region and the trench device isolation region alongside the channel sub-region; etching the trench device isolation region that is uncovered by the mask pattern in order to form a depression as far as a first depth using the first mask pattern as an etching mask; etching the channel sub-region in order to form a gate trench having a second depth, which is deeper than the first depth, using the mask pattern as an etching mask, and forming a recessed gate that fills the gate trench.
Problems in trench transistors of this type are caused by the overlap between the vertical gate and the highly doped source/drain regions. Said overlap causes high electric fields, which cause leakage currents in the switched-off state of the transistor. Moreover, depth or recess fluctuations have a great effect on the current in the switched-on state, since the transistor connection becomes poor if the source/drain doping regions no longer extend below the gate.